In recent years, personal computers have pushed into the field of work stations with intent to realize alternate for large-size computers by the network configuration of work stations. Also, an architecture for realizing a low-cost and high-speed graphic processing has recently been needed with the advance of home amusement equipments. In particular, a modified sprite processing for freely mapping source data of rectangles forms the basis of a three-dimensional graphics processing and is expected to have a drawing performance on the order of several ten thousands of polygons per second in order to realize more real display.
In order to improve the drawing performance of graphic LSI, a labor is taken for an improvement in the rate of data transfer between the graphic LSI and a frame buffer. A method for improving the data transfer rate includes (1) a method in which a high-speed interface is used and (2) a method in which a data bus width between the graphic LSI and the frame buffer is enlarged.
In the case of the method (1), the improvement in data transfer rate is realized using a DRAM provided with a high-speed page mode or a synchronous DRAM. The method using the synchronous DRAM is disclosed by JP-A-7-160249.
In the case of the method (2), the improvement in data transfer rate is realized by incorporating a frame buffer and a graphics controller in one chip with 128 bits or the like as the bit width of an internal bus. An example having a DRAM and a graphics controller incorporated in one chip is disclosed by "DEVELOPMENT OF GRAPHIC LSI HAVING FRAME BUFFER INCORPORATED THEREIN", Nikkei Electronics, p. 17 (Apr. 10, 1995) and "ONE-CHIP IMPLEMENTATION WITH LOGIC--DRAM FORMS CORE OF SYSTEM", Nikkei Microdevice, pp. 44-65 (March, 1996).
In the frame buffer incorporated graphic LSI disclosed by Nikkei Electronics, a portion of a 16-Mbit general purpose standard DRAM corresponding to 9 Mbits is removed and thereinstead replaced by a logic circuit including a controller. Regarding a DRAM incorporated graphic controller disclosed by Nikkei Microdevice, this reference has no specific disclosure excepting that the DRAM is incorporated.